Electronic Design, Test and Reliability Laboratory
The continuing scaling of circuit technology enables the integration of complete systems and even complete computer multi-clusters on a single chip. At the same time, very deep sub-micron and nanometer devices are subjected to a growing number and types of manufacturing as well as wear-out defects. The Electronic Design, Test and Reliability laboratory conducts research in the areas of computer aided design, testing and reliability of modern VLSI circuits and systems. Research focuses on state-of-the-art CAD algorithms for automatic testing, diagnosis, and verification, applicable to large-scale VLSI circuits as well as reusable embedded cores integrated into whole chip-level architectures such as SoCs, NoCs, and large-scale on-chip multiprocessors. On-going topics of research include automatic test generation and diagnosis techniques for various fault types (including timing and other deep-submicron/nanometer induced faults), circuit testability analysis (sensitization and hazard detection analysis), design for testability and diagnosis, microprocessor test, semi-formal methods for logic and timing verification and analysis, and symbolic techniques for test and verification (BDDs and SAT). We also have a strong interest in fault tolerance and reliability, especially for next-generation VLSI systems such as large-scale multicore chips. The laboratory is extensively equipped, including high-end servers/workstations and state-of the-art CAD tools (Synopsys, Cadence, and Mentor Graphic) for development and simulation purposes, as well as several FPGA-based prototyping systems and high-end logic analyzers.