Maria K. Michael received B.S. and M.S. degrees in Computer Science from Southern Illinois University in 1996 and 1998, respectively. She worked as a Research Assistant for the Electrical and Computer Engineering (ECE) Department of the University of Arizona, Tucson, during 1998-1999, and for the ECE Department of Southern Illinois University during 1999-2002, where she completed the Ph.D. degree in Engineering Sciences (specialization in Computer Engineering). She taught as a Lecturer at the ECE Department at Southern Illinois University during 2001-2002, and as an Assistant Professor of Computer Science and Engineering at the University of Notre Dame during 2002-2003. She joined the Electrical and Computer Engineering Department at the University of Cyprus in 2003. Her research interests are in the area of Computer-Aided Design for the design, test and reliability of modern digital VLSI circuits and embedded systems, including SoCs, NoCs and Chip Multiprocessors. Current focus is on test and diagnosis for various faults (including timing and other deep-submicron/nanometer induced faults), circuit testability analysis (sensitization and hazard detection analysis), testable design, microprocessor test, semi-formal methods for logic and timing verification and analysis, symbolic techniques for test and verification (BDDs and SAT), and graph theory and algorithms. Dr. Michael is a Member of the IEEE (Computer Society, Circuits and Systems Society, Test Technology Technical Council, Society of Women Engineers) and the ACM (Special Interest Group on Design Automation) and a reviewer for a number of scholarly journals and international conferences.

Design & Test automation for VLSI and embedded systems, including SoCs, NoCs and multi-core designs: testing and fault diagnosis; design for testability; microprocessor test; fault tolerance and reliability; test-based/semi-formal verification and timing analysis; decision diagrams and SAT.

S. Neophytou and M. K. Michael, "Test Set Generation with a Large Number of Unspecified Bits Using Static and Dynamic Techniques", IEEE Transactions on Computers, 2010.

K. Christou, M. K. Michael, and S. Tragoudas, "On the Use of ZBDDs for Implicit and Compact Critical Path Delay Fault Test Generation", Journal of Electronic Testing: Theory and Applications, 2008.

S. Neophytou, M. K. Michael, and S. Tragoudas, “Functions for Quality Transition Fault Tests and their Applications in Test Set Enhancement,” IEEE Transactions Computer-Aided Design of Integrated Circuits and Systems, 2006.

M. K. Michael and S. Tragoudas, “Function-based Compact Test Pattern Generation for Path Delay Faults,” IEEE Transactions on Very Large Scale Integration, 2005.

M. K. Michael, T. Haniotakis, and S. Tragoudas, “A Unified Framework for Generating Propagation Functions for Logic Errors and Events,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2004.

S. Padmanaban, M. K. Michael, and S. Tragoudas, “Exact Path Delay Fault Coverage with Fundamental Zero-Suppressed BDD Operations," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2003.

M. K. Michael and S. Tragoudas, “ATPG Tools for Delay Faults at the Functional level,” ACM Transactions On Design Automation of Electronic Systems, 2002.

Προσωπική Ιστοσελίδα: http://ucy.ac.cy/~mMichael.aspx