PUBLICATIONS

Books

[B1] C.A. Nicopoulos, N. Vijaykrishnan and C.R. Das, “Network-on-Chip Architectures: A Holistic Design Exploration,” Lecture Notes in Electrical Engineering Book Series, Springer, October 2009. ISBN: 978-90- 481-3030-6.
[Published by Springer as part of the European Design and Automation Association (EDAA) 2008-09 Outstanding Ph.D. Dissertation Award]

Book Chapters

[BC3] D. Zoni, P. Englezakis, K. Chrysanthou, A. Canidio, A. Prodromou, A. Panteli, C. Nicopoulos, G. Dimitrakopoulos, Y. Sazeides, and W. Fornaciari, “Monitor and Knob Techniques in Network-on-Chip Architectures,” Chapter in the book Harnessing Performance Variability in Embedded and High-performance Many/Multi-core Platforms – A Cross-layer Approach, Springer, Summer 2018.

[BC2] M.A. Skitsas, C. Nicopoulos, M.K. Michael, P. Bernardi, and E. Sanchez, “Self-testing of multi-core processors,” Chapter 15 in the book Many Core Computing: Hardware and Software, Institution of Engineering and Technology (IET) Publishing, Summer 2018.

[BC1] T. Theocharides, C.A. Nicopoulos, K. Irick, N. Vijaykrishnan, and M. J. Irwin, “An Exploration of Hardware Architectures for Face Detection,” in the VLSI Handbook, Second Edition, CRC Press, Taylor & Francis Group, Chapter 83, 2007.

Journal Articles

[J28] K. Patsidis, D. Konstantinou, C. Nicopoulos, and G. Dimitrakopoulos, “A Low-Cost Synthesizable RISC-V Dual-Issue Processor Core Leveraging the Compressed Instruction Set Extension,” in Elsevier Journal of Microprocessors and Microsystems: Embedded Hardware Design (MICPRO), Volume 61, pp. 1-10, September 2018.

[J27] I. Seitanidis, C. Nicopoulos, and G. Dimitrakopoulos, “Automatic Generation of Peak-Power Traffic for Networks-on-Chip,” in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), available online since February 2018, DOI: 10.1109/TCAD.2018.2801223.

[J26] M.A. Skitsas, C. Nicopoulos, and M.K. Michael, “Exploring System Availability during Software-Based Self-Testing of Multi-core CPUs,” in Springer Journal of Electronic Testing – Theory and Applications (JETTA), Volume 34, Issue 1, pp. 67-81, February 2018.

[J25] A. Psarras, S. Moisidis, C. Nicopoulos, and G. Dimitrakopoulos, “Networks-on-Chip with Double-Data-Rate Links,” in IEEE Transactions on Circuits and Systems I (TCAS-I), Volume 64, Issue 12, pp. 3103-3114, December 2017.

[J24] A. Savva, T. Theocharides, and C. Nicopoulos, “A Design Space Exploration Framework for ANN-Based Fault Detection in Hardware Systems,” in Journal of Electrical and Computer Engineering, Volume 2017, Article ID: 9361493, Digital Object Identifier (DOI): 10.1155/2017/9361493, December 2017.

[J23] A. Psarras, M. Paschou, C. Nicopoulos, and G. Dimitrakopoulos, “A Dual-Clock Multiple-Queue Shared Buffer,” in IEEE Transactions on Computers (TC), Volume 66, Issue 10, pp. 1809-1815, October 2017.

[J22] D. Zoni, A. Canidio, W. Fornaciari, P. Englezakis, C. Nicopoulos, and Y. Sazeides, “BlackOut: Enabling fine-grained power gating of buffers in Network-on-Chip routers,” in Elsevier Journal of Parallel and Distributed Computing (JPDC), Volume 104, pp. 130-145, June 2017.

[J21] J. Park, S. Baek, H.G. Lee, C. Nicopoulos, V. Young, J. Lee, and J. Kim, “HoPE: Hot-cacheline Prediction for Dynamic Early Decompression in Compressed LLCs,” in ACM Transactions on Design Automation of Electronic Systems (TODAES), Volume 22, Issue 3, Article No. 40, April 2017.

[J20] A. Psarras, I. Seitanidis, C. Nicopoulos, and G. Dimitrakopoulos, “ShortPath: A Network-on-Chip Router with Fine-Grained Pipeline Bypassing,” in IEEE Transactions on Computers (TC), Volume 65, Issue 10, pp. 3136-3147, October 2016.

[J19] M. Alam, Z.C. Lee, C. Nicopoulos, K.H. Lee, J. Kim, and J. Lee, “SBBox: A Tamper-Resistant Digital Archiving System,” in International Journal of Cyber-Security and Digital Forensics (IJCSDF), Volume 5, Issue 3, pp. 122-131, August 2016.

[J18] K. Chrysanthou, P. Englezakis, A. Prodromou, A. Panteli, C. Nicopoulos, Y. Sazeides, and G. Dimitrakopoulos, “An Online and Real-Time Fault Detection and Localization Mechanism for Network-on- Chip Architectures,” in ACM Transactions on Architecture and Code Optimization (TACO), Volume 13, Issue 2, June 2016.

[J17] A. Psarras, J. Lee, I. Seitanidis, C. Nicopoulos, and G. Dimitrakopoulos, “PhaseNoC: Versatile Network Traffic Isolation Through TDM-Scheduled Virtual Channels,” in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), Volume 35, Issue 5, pp. 844-857, May 2016.

[J16] M.A. Skitsas, C. Nicopoulos, and M.K. Michael, “DaemonGuard: Enabling O/S-Orchestrated Fine- Grained Software-Based Selective-Testing in Multi-/Many-Core Microprocessors,” in IEEE Transactions on Computers (TC), Volume 65, Issue 5, pp. 1453-1466, May 2016.

[J15] M. Kleanthous, Y. Sazeides, E. Ozer, C. Nicopoulos, P. Nikolaou, and Z. Hadjilambrou, “Toward Multi- Layer Holistic Evaluation of System Designs,” in IEEE Computer Architecture Letters (CAL), Volume 15, Issue 1, January–June 2016.

[J14] I. Seitanidis, A. Psarras, K. Chrysanthou, C. Nicopoulos, and G. Dimitrakopoulos, “ElastiStore: Flexible Elastic Buffering for Virtual-Channel-Based Networks on Chip,” in IEEE Transactions on Very Large Scale Integration Systems (TVLSI), Vol. 23, Issue 12, pp. 3015-3028, December 2015.

[J13] S. Kang, C. Nicopoulos, A. Gavriloska, and J. Kim, “Subtleties of Run-Time Virtual Address Stacks,” in IEEE Computer Architecture Letters (CAL), Vol. 14, Issue 2, pp. 152-155, July–December 2015.

[J12] S. Baek, H.G. Lee, C. Nicopoulos, J. Lee, and J. Kim, “Size-Aware Cache Management for Compressed Cache Architectures,” in IEEE Transactions on Computers (TC), Vol. 64, Issue 8, pp. 2337-2352, August 2015.

[J11] S. Baek, H.G. Lee, C. Nicopoulos, and J. Kim, “Designing Hybrid DRAM/PCM Main Memory Systems Utilizing Dual-Phase Compression,” in ACM Transactions on Design Automation of Electronic Systems (TODAES), Vol. 20, Issue 1, Article No. 11, November 2014.

[J10] J. Lee, C. Nicopoulos, H.G. Lee, and J. Kim, “Centaur: a Hybrid Network-on-Chip Architecture Utilizing Micro-Network Fusion,” in Springer Journal of Design Automation for Embedded Systems (DAEM), Volume 18, Issue 3, pp. 121-139, September 2014.

[J9] J. Lee, C. Nicopoulos, H.G. Lee, and J. Kim, “TornadoNoC: A Lightweight and Scalable On-Chip Net- work Architecture for the Many-Core Era,” in ACM Transactions on Architecture and Code Optimization (TACO), Vol. 10, Issue 4, Article No. 56, December 2013.

[J8] J. Lee, C. Nicopoulos, H.G. Lee, and J. Kim, “Sharded Router: A Novel On-Chip Router Architecture Employing Bandwidth Sharding and Stealing,” in Elsevier Journal of Parallel Computing (PARCO), Vol. 39, Issue 9, pp. 372-388, September 2013.

[J7] A. Vitkovskiy, V. Soteriou, and C. Nicopoulos, “Dynamic fault-tolerant routing algorithm for networks- on-chip based on localised detouring paths,” in IET Computers and Digital Techniques Journal, Vol. 7, Issue 2, pp. 93-103, March 2013.

[J6] J. Lee, C. Nicopoulos, H.G. Lee, S. Panth, S.K. Lim, and J. Kim, “IsoNet: Hardware-based Job Queue Management for Manycore Architectures,” in IEEE Transactions on Very Large Scale Integration Systems (TVLSI), Vol. 21, Issue 6, pp. 1080-1093, June 2013.

[J5] B. Grot, D. Hardy, P. Lotfi-Kamran, C. Nicopoulos, Y. Sazeides, and B. Falsafi, “Optimizing Datacenter TCO with Scale-Out Processors,” in IEEE Micro, Vol. 32, Issue 5, September-October 2012.

[J4] A. Vitkovskiy, V. Soteriou, and C. Nicopoulos, “A Dynamically Adjusting Gracefully Degrading Link- Level Fault-Tolerant Mechanism for NoCs,” in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), Vol. 31, Issue 8, pp. 1235-1248, August 2012.

[J3] F. Wang, Y. Chen, C.A. Nicopoulos, X. Wu, Y. Xie, and N. Vijaykrishnan, “Variation-aware Task and Communication Mapping for MPSoC Architecture,” in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), Vol. 30, Issue 2, pp. 295-307, February 2011.

[J2] C.A. Nicopoulos, S. Srinivasan, A. Yanamandra, D. Park, N. Vijaykrishnan, C.R. Das, and M.J. Irwin, “On the Effects of Process Variation in Network-on-Chip Architectures,” in the IEEE Transactions on Dependable and Secure Computing (TDSC), Vol. 7, Issue 3, pp. 240-254, July-September 2010.

[J1] A. Cevrero, P. Athanasopoulos, H.P. Afshar, A.K. Verma, P. Brisk, F.K. Gurkaynak, C.A. Nicopoulos, Y. Leblebici, and P. Ienne, “The Field-Programmable Compressor Tree: a Programmable IP Core for Improved FPGA Arithmetic Performance,” in the ACM Transactions on Reconfigurable Technology and Systems (TRETS), Vol. 2, Issue 2, Article 13, pp. 13:1-13:36, June 2009.

Conference Proceedings

[C53] D. Konstantinou, A. Psarras, C. Nicopoulos, and G. Dimitrakopoulos, “Low-Power Dual-Edge-Triggered Synchronous Latency-Insensitive Systems,” in Proceedings of the IEEE International Conference on Modern Circuits and Systems Technologies (MOCAST), May 2018.

[C52] J. Lee, M. Debnath, A. Patki, M. Hasan, and C. Nicopoulos, “Hardware-based Online Self-diagnosis for Faulty Device Identification in Large-scale IoT Systems,” in Proceedings of ACM/IEEE International Conference on Internet-of-Things Design and Implementation (IoTDI), April 2018.

[C51] N. Zompakis, M. Noltsis, L. Ndreu, Z. Hadjilambrou, P. Englezakis, P. Nikolaou, A. Portero, S. Libutti, G. Massari, F. Sassi, A. Bacchini, C. Nicopoulos, Y. Sazeides, R. Vavrik, M. Golasowski, J. Sevcik, V. Vondrak, F. Catthoor, W. Fornaciari, and D. Soudris, “HARPA: Tackling Physically Induced Performance Variability,” in Proceedings of Design Automation and Test in Europe (DATE) Conference, March 2017.

[C50] M. Debnath, D. Konstatinou, C. Nicopoulos, G. Dimitrakopoulos, W.M. Lin, and J. Lee, “Low-Cost Congestion Management in Networks-on-Chip Using Edge and In-Network Traffic Throttling,” in Proceedings of the International Workshop on Advanced Interconnect Solutions and Technologies for Emerging Com- puting Systems (AISTECS) (held in conjunction with the HiPEAC Conference), January 2017.

[C49] A. Psarras, S. Moisidis, C. Nicopoulos, and G. Dimitrakopoulos, “RapidLink: a Network-on-Chip Ar- chitecture with Double-Data-Rate Links,” in Proceedings of the IEEE International Conference on Electronics, Circuits and Systems (ICECS), December 2016.

[C48] I. Seitanidis, C. Nicopoulos, and G. Dimitrakopoulos, “PowerMax: an automated methodology for generating peak-power traffic in networks-on-chip,” in Proceedings of the IEEE Symposium on Networks- on-Chip (NOCS), September 2016.
[Best Paper Award Nominee]

[C47] A. Psarras, J. Lee, P.M. Mattheakis, C. Nicopoulos, and G. Dimitrakopoulos, “A Low-Power Network- on-Chip Architecture for Tile-based Chip Multi-Processors,” in Proceedings of the ACM Great Lakes Sym- posium on VLSI (GLSVLSI), May 2016.

[C46] M. Paschou, A. Psarras, C. Nicopoulos, and G. Dimitrakopoulos, “CrossOver: Clock Domain Crossing under Virtual-Channel Flow Control,” in Proceedings of Design Automation and Test in Europe (DATE) Conference, March 2016.

[C45] M. Skitsas, C. Nicopoulos, and M.K. Michael, “Toward efficient check-pointing and rollback under on-demand SBST in chip multi-processors,” in Proceedings of the IEEE International On-Line Testing Sym- posium (IOLTS), July 2015.

[C44] A. Panteloukas, A. Psarras, C. Nicopoulos, and G. Dimitrakopoulos, “Timing-resilient Network-on-Chip architectures,” in Proceedings of the IEEE International On-Line Testing Symposium (IOLTS), July 2015.

[C43] D. Rodopoulos, S. Corbetta, G. Massari, S. Libutti, F. Catthoor, Y. Sazeides, C. Nicopoulos, A. Portero, E. Cappe, R. Vavrik, V. Vondrak, D. Soudris, F. Sassi, A. Fritsch, and W. Fornaciari, “HARPA: Solutions for Dependable Performance under Physically Induced Performance Variability,” in Proceedings of the IEEE International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation (SAMOS), July 2015.

[C42] D. Rodopoulos, Y. Sazeides, F. Catthoor, C. Nicopoulos, and D. Soudris, “Sensitivity of SRAM Cell Most Probable SNM Failure Point to Time-Dependent Variability,” in Proceedings of the 11th Workshop on Silicon Errors in Logic – System Effects (SELSE), March 2015.

[C41] A. Psarras, I. Seitanidis, C. Nicopoulos, and G. Dimitrakopoulos, “PhaseNoC: TDM scheduling at the virtual-channel level for efficient network traffic isolation,” in Proceedings of Design Automation and Test in Europe (DATE) Conference, March 2015.
[Best Paper Award – Europe’s premiere and biggest electronic system design & test conference – Acceptance Rate: 22.4% (for long/short presentations)]

[C40] M. Skitsas, C. Nicopoulos, and M.K. Michael, “Exploring check-pointing and rollback recovery under selective SBST in Chip Multi- Processors,” in Proceedings of the Workshop on Manufacturable and Dependable Multicore Architectures at Nanoscale (MEDIAN), March 2015.

[C39] M. Skitsas, C. Nicopoulos, and M.K. Michael, “Exploration of System Availability During Software- Based Self-Testing in Many-core Systems under Test Latency Constraints,” in Proceedings of the IEEE Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT), October 2014.

[C38] I. Seitanidis, A. Psarras, E. Kalligeros, C. Nicopoulos, and G. Dimitrakopoulos, “ElastiNoC: A Self- Testable Distributed VC-based Network-on-Chip Architecture,” in Proceedings of the IEEE Symposium on Networks-on-Chip (NOCS), September 2014.

[C37] I. Seitanidis, A. Psarras, G. Dimitrakopoulos, and C. Nicopoulos, “ElastiStore: An elastic buffer ar- chitecture for Network-on-Chip routers,” in Proceedings of Design Automation and Test in Europe (DATE) Conference, March 2014.

[C36] J. Lee, C. Nicopoulos, G.H. Oh, S.W. Lee, and J. Kim, “Hardware-assisted Intrusion Detection by Pre- serving Reference Information Integrity,” in Proceedings of the 13th International Conference on Algorithms and Architectures for Parallel Processing (ICA3PP), December 2013.

[C35] M.A. Skitsas, C. Nicopoulos, and M.K. Michael, “DaemonGuard: O/S-assisted selective software-based Self-Testing for multi-core systems,” in Proceedings of the IEEE Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT), October 2013.

[C34] J. Lee, C. Nicopoulos, S.J. Park, M. Swaminathan, and J. Kim, “Do We Need Wide Flits in Networks- On-Chip?” in Proceedings of IEEE Computer Society Annual Symposium on VLSI (ISVLSI), August 2013.

[C33] G. Dimitrakopoulos, N. Georgiadis, C. Nicopoulos, E. Kalligeros, “Switch Folding: Network-on-Chip Routers with Time-Multiplexed Output Ports,” in Proceedings of the Design, Automation, and Test in Europe (DATE) Conference, March 2013.

[C32] S. Baek, H.G. Lee, C. Nicopoulos, J. Lee, and J. Kim, “ECM: Effective Capacity Maximizer for High- Performance Compressed Caching,” in Proceedings of the 19th IEEE International Symposium on High Performance Computer Architecture (HPCA), 12 pages, February 2013.
[Flagship conference in Computer Architecture – Acceptance Rate: 20.5%]

[C31] A. Prodromou, A. Panteli, C. Nicopoulos, and Y. Sazeides, “NoCAlert: An On-Line and Real-Time Fault Detection Mechanism for Network-on-Chip Architectures,” in Proceedings of the 45th Annual International Symposium on Microarchitecture (MICRO), 12 pages, December 2012.
[HiPEAC 2012 Paper Award – Flagship conference in Computer Architecture – Acceptance Rate: 17.5%]

[C30] D. Milojevic, S. Idgunji, D. Jevdjic, E. Ozer, P. Lotfi-Kamran, A. Panteli, A. Prodromou, C. Nicopoulos, D. Hardy, B. Falsafi, and Y. Sazeides, “Thermal Characterization of Cloud Workloads on a Low-power Server-on-Chip,” in Proceedings of the IEEE International Conference on Computer Design (ICCD), October 2012.

[C29] M. Evripidou, C. Nicopoulos, V. Soteriou, and J. Kim, “Virtualizing Virtual Channels for Increased Network-on-Chip Robustness and Upgradeability,” in Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI), pp. 21-26, August 2012.

[C28] H.G. Lee, S. Baek, J. Kim, and C. Nicopoulos, “A Compression-based Hybrid MLC/SLC Management Technique for Phase-Change Memory Systems,” in Proceedings of the IEEE Computer Society Annual Sym- posium on VLSI (ISVLSI), pp. 386-391, August 2012.

[C27] M. Skitsas, C. Nicopoulos, and M. Michael, “Toward Selective Software-Based Self-Testing in Future Multi-Core Microprocessors,” in Proceedings of the Workshop on Manufacturable and Dependable Multicore Architectures at Nanoscale (MEDIAN), pp. 71-75, June 2012.

[C26] J. Lee, H.G. Lee, S. Ha, J. Kim, and C. Nicopoulos, “A Programmable Processing Array Architecture Supporting Dynamic Task Scheduling and Module-Level Prefetching,” in Proceedings of the ACM Inter- national Conference on Computing Frontiers, pp. 153-162, May 2012.

[C25] S. Baek, H.G. Lee, C. Nicopoulos, and J. Kim, “A Dual-Phase Compression Mechanism for Hybrid DRAM/PCM Main Memory Architectures,” in Proceedings of the Great Lakes Symposium on VLSI (GLSVLSI), pp. 345-350, May 2012.

[C24] J. Lee, C. Nicopoulos, H.G. Lee, D. Shin, and J. Kim, “Hermes: Scalable Load Distribution Engine for General-Purpose Computing on Graphics Processing Units (GPGPU),” in Proceedings of the International Conference on Electronics, Information, and Communication (ICEIC), pp. N/A (digital only), February 2012.

[C23] A. Vitkovskiy, V. Soteriou, and C. Nicopoulos, “A Highly Robust Distributed Fault-Tolerant Routing Algorithm for NoCs with Localized Rerouting,” in Proceedings of the Workshop on Interconnection Network Architectures: On-Chip, Multi-Chip (INA-OCMC) (held in conjunction with the HiPEAC Conference), pp.29-32, January 2012.

[C22] H.G. Lee, S. Baek, C. Nicopoulos, and J. Kim, “An energy- and performance-aware DRAM cache archi- tecture for hybrid DRAM/PCM main memory systems,” in Proceedings of the IEEE International Confer- ence on Computer Design (ICCD), pp. 381-387, October 2011.

[C21] S. Kang, C. Nicopoulos, H.G. Lee, and J. Kim, “A High-Performance and Energy-Efficient Virtually Tagged Stack Cache Architecture for Multi-core Environments,” In Proceedings of the IEEE International Conference on High Performance Computing and Communications (HPCC), pp. 58-67 (10 pages), September 2011.
[Best Paper Award]

[C20] J. Lee, C.A. Nicopoulos, Y. Lee, H. Lee, and J. Kim, “Hardware-based Job Queue Management for Many- core Architectures and OpenMP Environments,” in Proceedings of the International Parallel & Distributed Processing Symposium (IPDPS), pp. 407-418 (12 pages), May 2011.
[Best Paper Award Nominee – Architecture Track – Acceptance Rate: 19.6%]

[C19] M. Diao, C.A. Nicopoulos, and J. Kim, “Large-Scale Semantic Concept Detection on Manycore Platforms for Multimedia Mining,” in Proceedings of the International Parallel & Distributed Processing Symposium (IPDPS), pp. 384-394 (11 pages), May 2011.
[Acceptance Rate: 19.6%]

[C18] A. Vitkovskiy, V. Soteriou, and C.A. Nicopoulos, “A Fine-Grained Link-Level Fault Tolerant Mechanism for NoCs,” in Proceedings of the IEEE International Conference on Computer Design (ICCD), pp. 447-454, October 2010.

[C17] E. Ozer, K. Flautner, S. Idgunji, A. Saidi, Y. Sazeides, B. Ahsan, N. Ladas, C. Nicopoulos, I. Sideris, B. Falsafi, A. Adileh, M. Ferdman, P. Lotfi-Kamran, M. Kuulusa, P. Marchal, and N. Minas, “Euro- Cloud: Energy-conscious 3D Server-on-Chip for Green Cloud Services,” in Proceedings of 2nd Workshop on Architectural Concerns in Large Datacenters (held in conjunction with the ISCA Conference), June 2010.

[C16] S. Hosein, A. Cevrero, P. Brisk, C.A. Nicopoulos, F.K. Gurkaynak, Y. Leblebici, and P. Ienne, “Design Space Exploration for Field Programmable Compressor Trees,” in Proceedings of the International Con- ference on Compilers, Architecture, and Synthesis for Embedded Systems (CASES), pp. 207-216 (10 pages), 2008.

[C15] N. Soundararajan, A. Yanamandra, C.A. Nicopoulos, N. Vijaykrishnan, A. Sivasubramaniam, and M.J. Irwin, “Analysis and solutions to Issue Queue Process Variation,” in Proceedings of the International Conference on Dependable Systems and Networks (DSN), pp. 11-21 (11 pages), 2008.

[C14] R. Das, A.K. Mishra, C.A. Nicopoulos, D. Park, N. Vijaykrishnan, R. Iyer, M.S. Yousif, C.R. Das, “Per- formance and Power Optimization through Data Compression in Network-on-Chip Architectures,” in Proceedings of the 14th International Symposium on High-Performance Computer Architecture (HPCA), pp. 215-225 (12 pages), 2008.
[Flagship conference in Computer Architecture – Acceptance Rate: 19%]

[C13] C.A. Nicopoulos, A. Yanamandra, S. Srinivasan, N. Vijaykrishnan, and M.J. Irwin, “Variation-Aware Low-Power Buffer Design,” in Proceedings of the 41st Asilomar Conference on Signals, Systems, and Comput- ers, pp. 1402-1406, 2007.

[C12] F. Wang, C.A. Nicopoulos, X. Wu, Y. Xie, and N. Vijaykrishnan, “Variation-aware Task Allocation and Scheduling for MPSoC,” in Proceedings of the International Conference on Computer-Aided Design (ICCAD), pp. 598-603, 2007.

[C11] D. Park, R. Das, C.A. Nicopoulos, J. Kim, N. Vijaykrishnan, R. Iyer, and C. R. Das, “Design of a Dy- namic Priority-Based Fast Path Architecture for On-Chip Interconnects,” in Proceedings of the 15th IEEE Symposium on High-Performance Interconnects (Hot Interconnects), pp. 15-20, 2007.

[C10] J. Kim, C.A. Nicopoulos, D. Park, R. Das, Y. Xie, N. Vijaykrishnan, and C.R. Das, “A Novel Dimensionally- Decomposed Router for On-Chip Communication in 3D Architectures,” in Proceedings of the 34th Annual International Symposium on Computer Architecture (ISCA), pp. 138-149 (12 pages), 2007.
[Flagship conference in Computer Architecture – Acceptance Rate: 22.5%]

[C9] C.A. Nicopoulos, D. Park, J. Kim, N. Vijaykrishnan, M.S. Yousif, and C.R. Das, “ViChaR: A Dynamic Virtual Channel Regulator for Network-on-Chip Routers,” in Proceedings of the 39th Annual International Symposium on Microarchitecture (MICRO), pp. 333-344 (12 pages), 2006.
[Flagship conference in Computer Architecture – Acceptance Rate: 24%]

[C8] D. Park, C.A. Nicopoulos, J. Kim, N. Vijaykrishnan, and C.R. Das, “A Distributed Multi-Point Net- work Interface for Low-Latency, Deadlock-Free On-Chip Interconnects,” in Proceedings (electronic) of the International Conference on Nano-Networks (Nano-Net), 2006.

[C7] F. Li, C.A. Nicopoulos, T. Richardson, Y. Xie, N. Vijaykrishnan, and M. Kandemir, “Design and Man- agement of 3D Chip Multiprocessors Using Network-in-Memory,” in Proceedings of the 33rd Annual In- ternational Symposium on Computer Architecture (ISCA), pp. 130-141 (12 pages), 2006.
[Flagship conference in Computer Architecture – Acceptance Rate: 13%]

[C6] J. Kim, C.A. Nicopoulos, D. Park, N. Vijaykrishnan, M.S. Yousif, and C.R. Das, “A Gracefully Degrading and Energy-Efficient Modular Router Architecture for On-Chip Networks,” in Proceedings of the 33rd Annual International Symposium on Computer Architecture (ISCA), pp. 4-15 (12 pages), 2006.
[Flagship conference in Computer Architecture – Acceptance Rate: 13%]

[C5] D. Park, C.A. Nicopoulos, J. Kim, N. Vijaykrishnan, and C.R. Das, “Exploring Fault-Tolerant Network- on-Chip Architectures,” in Proceedings of the International Conference on Dependable Systems and Networks (DSN), pp. 93-102 (10 pages), 2006.

[C4] J. Kim, D. Park, C.A. Nicopoulos, N. Vijaykrishnan, and C.R. Das, “Performance Enhancement through Early Release and Buffer Optimization in Network-on-Chip Router Architectures,” in Special Workshop on Future Interconnects and Networks on Chip at the Design, Automation and Test in Europe (DATE) Conference, 2006.

[C3] T.D. Richardson, C.A. Nicopoulos, D. Park, N. Vijaykrishnan, Yuan Xie, C.R. Das, and V. Degalahal, “A Hybrid SoC Interconnect with Dynamic TDMA-Based Transaction-Less Buses and On-Chip Networks,” in Proceedings of the 19th International Conference on VLSI Design, pp. 657-664, 2006.

[C2] J. Kim, D. Park, C.A. Nicopoulos, N. Vijaykrishnan, and C.R. Das, “Design and analysis of an NoC architecture from performance, reliability and energy perspective,” in Proceedings of the Symposium on Architectures for Networking and Communications Systems (ANCS), pp. 173-182, 2005.

[C1] J. S. Kim, C.A. Nicopoulos, N. Vijaykrishnan, Y. Xie, and E. Lattanzi, “A Probabilistic Model for Soft- Error Rate Estimation in Combinational Logic,” in Proceedings of the International Workshop on Probabilistic Analysis Techniques for Real Time and Embedded Systems (PARTES), 2004.

Technical Reports

[TR1] J. Kim, C.A. Nicopoulos, D. Park, N. Vijaykrishnan, and C.R. Das, “A Fine-Grained Modular Architecture for System-on-Chip Networks,” Technical Report, CSE-06-013, Department of Computer Science and Engineering, The Pennsylvania State University, University Park, PA, USA, 2006.

Theses

[Th2] C.A. Nicopoulos, “Network-on-Chip Architectures: A Holistic Design Exploration,” Ph.D. Thesis (under N. Vijaykrishnan), Department of Electrical Engineering, The Pennsylvania State University, University Park, PA, 2007.

[Th1] C.A. Nicopoulos, “Smart Antennas for Wireless Communications,” Undergraduate Honors Thesis (under J.F. Doherty), Department of Electrical Engineering, The Pennsylvania State University, University Park, PA, 2003.

Conference Presentations & Invited Talks

[P14] “A Network-on-Chip Router Architecture with Unified and Dynamic Buffer Management,” Graduate Seminar of the Department of Electrical and Computer Engineering, University of Cyprus, Nicosia, Cyprus, April 2010.

[P13] “Dynamic Virtual Channel Regulation and Buffering for On-Chip Networks,” at the Interconnects Clus- ter Meeting of the International Conference on High Performance and Embedded Architectures and Compilers (HiPEAC), January 2009, Paphos, Cyprus.

[P12] “Network-on-Chip Architectural Exploration,” Poster Presentation at the International Conference on High

Performance and Embedded Architectures and Compilers (HiPEAC), January 2009, Paphos, Cyprus.

[P11] “The Effects of Process Variation on Network-on-Chip Architectures,” Guest Lecture at the Xi Computer Architecture Research Group Seminar of the Department of Computer Science, University of Cyprus, Nicosia, Cyprus, October 2008.

[P10] “Exploring On-Chip Interconnection Network Architectures,” Poster Presentation at the European Design and Automation Association (EDAA) Ph.D. Forum at the DATE Conference, Munich, Germany, March 2008.

[P9] “The New Face of the On-Chip Interconnect,” at the Interconnects Cluster Meeting of the International Con- ference on High Performance and Embedded Architectures and Compilers (HiPEAC), January 2008, Goteborg, Sweden.

[P8] “ViChaR: A Dynamic Virtual Channel Regulator and Unified Buffer Structure for On-Chip Routers,” Focus Center Research Program (FCRP) e-Connect Seminar (Given to eminent semiconductor industry spon- sors by top US research institutions – very competitive presenter selection process), April 2007.

[P7] “3D + NoC: An Emerging Interconnect Paradigm,” at Intel Corporation, Hillsboro, Oregon, USA, March 2007.

[P6] “ViChaR: A Dynamic Virtual Channel Regulator for Network-on-Chip Routers,” at the 39th Annual

International Symposium on Microarchitecture (MICRO), Orlando, Florida, USA, December 2006.

[P5] “Architectural Exploration in NoC Design,” at the GSRC Annual Symposium, San Jose, California, USA, September 2006.

[P4] “A Novel Decomposable Router Architecture for On-Chip Networks,” Graduate Seminar of the Depart- ment of Electrical and Computer Engineering, University of Cyprus, Nicosia, Cyprus, September 2006.

[P3] “A Gracefully Degrading and Energy-Efficient Modular Router Architecture for On-Chip Networks,” at the 33rd Annual International Symposium on Computer Architecture (ISCA), Boston, Massachusetts, USA, June 2006.

[P2] “A 3D Network-on-Chip Simulator,” at the GSRC Quarterly Workshop, Berkeley, California, USA, March 2006.

[P1] “HS3d: Hot Spot 3d,” at the GSRC Quarterly Workshop, Berkeley, California, USA, March 2006.